Finite State Machine Decomposition For Low Power

Finite State Machine Decomposition For Low Power. Monteiro, J.C.; Oliveria, A.L.; Design Automation Conference, 1998. Proceedings 15-19 Jun 1998 Page(s):758 - 763 Speaker: WEI-FU HUANG,98662001. Outline. Introduction Basic Definitions Related Work Decomposition of Finite State Machines
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Finite State Machine Decomposition For Low PowerMonteiro, J.C.; Oliveria, A.L.;Design Automation Conference, 1998. Proceedings15-19 Jun 1998 Page(s):758 - 763Speaker: WEI-FU HUANG,98662001Outline
  • Introduction
  • Basic Definitions
  • Related Work
  • Decomposition of Finite State Machines
  • Finite State Machine Decomposition for Low Power
  • Conclusions
  • References
  • Introduction
  • In static CMOS circuits, the probabilistic switching activity of nodes in the circuit is a good measure of the average power dissipation of the circuit.
  • The disabling of the input/state registers is decided on a clock-cycle basis and can be done either by using aregister load-enable signal or by gating the clock.
  • The original FSM is divided into two sub-FSMs
  • where one of them is significantly smaller than the other. Except for transitions that involve going from one state in one sub-machine to a state in the other, only one of the sub-machines needs to be clocked .
  • By selecting for the small sub-FSM a cluster of states in which the original FSM has a high probability of being in, most of the time we will be disabling all the state registers in the larger sub-FSM.
  • Basic Definitions
  • A finite state machine is defined in the standard was as a tuple M = (Σ,Δ,Q,qo, δ, λ) where Σ is a finite set of input symbols, Δ ≠φa finite set of output symbols,Q ≠φis a finite set of states, qo € Q is the “reset” state, δ (q,a): Q × Σ→Qis thetransition function, and λ(q,a) :
  • Q ×Σ → Δ is the output function.Related Work
  • So called power managementtechniques that shutdown blocks ofhardware for periods of time in which they are not producing useful data are effective methods to reduce the power consumption of a circuit.
  • A system-level approach is todentify idle periods for entire modules and turn off the clock lines forless modules for the duration of the idle periods.
  • The choice of the number of inputs to use for the pre-computation logic is critical.
  • The more inputs used the highest the probability the pre-computation logic will be active, thus disabling logic in the original logic block.
  • Decomposition of Finite State MachinesFig. 2. Structure of decomposed finite state machine.Fig. 3. State transition graph of the sequence detector.Fig. 4. STGs(State transition graph ) for the sequence detector after decomposition.Finite State Machine Decomposition for Low Power
  • The main objective of this work is to use finite state machine decomposition techniques to achieve low power dissipation.
  • The basic idea, described in this section, is to decompose the original machine into two machines, one of them with a reduced number of states and low power dissipation that performs needed computations for a large raction of the time.
  • Conclusions
  • The methodologyses well known decomposition techniques to obtain a state machineat, for the majority of the large examples tested, exhibits a muchnuller power dissipation than the original.
  • It is clear that the results obtained in this paper can be improvedif a more efficient implementation of the decomposition strategyis selected.
  • References
  • [1] M. Alidina, J. Monteiro, S. Devadas, A. Ghosh, and M. Papaefthymiou.Precomputation-Based Sequential Logic Optimization for Low Power.IEEE Transactions on VLSI Systems, 2(4):426-436, December 1994.
  • [2] L. Benini, P. Siegel, and G. De Micheli. Automatic Synthesis of
  • Low-Power Gated-Clock Finite-State Machines. IEEE Transactions onComputer-Aided Design, 15(6):63@643, June 1996.
  • [3]L. Benini, P. Vuillod, C. Coelho, and G. De Micheli. Synthesis of Low-
  • Power Partially-Clocked Systems from High-Level Specifications. In9th International Symposium on System Synthesis, November 1996.
  • [4]A. Chandrakasan and R. Brodersen. Low Power Digital CMOS Design.Kluwer Academic Publishers, 1995.
  • [5]S-H. Chow, Y-C. Ho, and T. Hwang. Low Power Realization of Finite
  • State Machines - A Decomposition Approach. ACM Transactions onDesign Automation of Electronic Systems, 1(3):3 15-340, July 1996.
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